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NT5TU64M8DE / nt5tu32m16dg 512mb ddr2 sdram ???????????????????? 1 ? rev 1.7 consumer dram jul / 2012 ? nanya technology corp . all rights reserved nanya technology corp. reserves the right to chan ge products and specifications without notice. feature cas latency frequency speed bins -3c/3ci* (ddr2-667-cl5) -ac/aci* (ddr2-800-cl5) -be* (ddr2-1066-cl7) -bd* (ddr2-1066-cl6) units parameter min. max. min. max. min. max. min. max. tck (avg.) clock frequency 125 333 125 400 125 533 125 533 mhz trcd ? 15 - 12.5 - 12.5 - 11.25 - ns trp ? 15 - 12.5 - 12.5 - 11.25 - ns trc ? 60 - 57.5 - 57.5 - 56.25 - ns tras ? 45 70k 45 70k 45 70k 45 70k ns tck (avg.) @ cl3 ? 5 8 5 8 5 8 5 8 ns tck (avg.) @ cl4 3.75 8 3.75 8 3.75 8 3.75 8 ns tck (avg.) @ cl5 3 8 2.5 8 2.5 8 2.5 8 ns tck (avg.) @ cl6 - - 2.5 8 2.5 8 1.875 8 ns tck (avg.) @ cl7 - - - - 1.875 8 1.875 8 ns *the timing specification of high speed bin is backward compatible with low speed bin z 1.8v 0.1v power supply voltage z 4 internal memory banks z programmable cas latency: 3, 4, 5 (-3c/-3ci/-ac/-aci/-bd/-be) 6 (-ac/-aci/-bd/-be) 7 (-bd/-be) z programmable additive latency: 0, 1, 2, 3, 4 5 z write latency = read latency -1 z programmable burst length: z 4 and 8 programmable sequential / interleave burst z ocd (off-chip driver impedance adjustment) z odt (on-die termination) z 4 bit prefetch architecture z data-strobes: bidi rectional, differential z support industrial grade temperature -40 ~95 operating temperature (-3ci/-aci) z 1kb page size for x8 2kb page size for x16 z strong and weak strengt h data-output driver z auto-refresh and self-refresh z power saving power-down modes z 7.8 s max. average periodic refresh interval z rohs compliance and halogen free z packages: 60-ball bga for x8 components 84-ball bga for x16 components free datasheet http:/// NT5TU64M8DE / nt5tu32m16dg 512mb ddr2 sdram ???????????????????? 2 ? rev 1.7 consumer dram jul / 2012 ? nanya technology corp . all rights reserved nanya technology corp. reserves the right to chan ge products and specifications without notice. description the 512mbit double-data-rate-2 (ddr2) drams is a high-speed cmos double data rate 2 sdram containing 536,870,912 bits. it is internally configured as a quad-bank dram. the 512mb chip is organized as 16mbit x 8 i/o x 4 bank or 8mbit x 16 i/o x 4 ba nk device. these synchronous devices achieve high speed double-data-rate transfer rates of up to 1066 mb/sec/pin for general applications. the chip is designed to comply with all key ddr2 dram key features: (1) posted cas with additive latency, (2) write latency = read latency -1, (3) normal and weak str ength data-output driver, (4) variable data-output impedance adjustment and (5) an odt (on- die termination) function. all of the control and addres s inputs are synchronized with a pair of exter nally supplied differential clocks. inputs are latched at the cross point of di fferential clocks (ck rising and ck falling). all i/os are synchr onized with a single ended dqs or differential dqs pair in a source synchronous fash ion. a 14 bit address bus for x8 organized components and a 13 bit address bus for x16 component is used to convey row, column, and bank address devices. these devices operate with a single 1.8v 0.1v po wer supply and are available in bga packages. free datasheet http:/// NT5TU64M8DE / nt5tu32m16dg 512mb ddr2 sdram ???????????????????? 3 ? rev 1.7 consumer dram jul / 2012 ? nanya technology corp . all rights reserved nanya technology corp. reserves the right to chan ge products and specifications without notice. pin configuration ? 60 balls bga package (x8) < top view> see the balls through the package a b c d e f g x 8 1 vdd dq4 nu,/rdqs vssq dq1 vssq vref cke a10/ ap 2 vss dm/rdqs vddq dq3 vss we ba 1 3 7 8 9 a3 vddq vdd dqs vssq dq0 vssq ck ck cs vssq dqs vddq vssdl ras cas vdd h j k l dq6 vddq vddl a7 a12 vdd ba0 a1 a5 a9 nc nc a11 a6 a2 dq2 a13 a8 a4 a0 dq7 vddq dq5 vss nc vss odt ? free datasheet http:/// NT5TU64M8DE / nt5tu32m16dg 512mb ddr2 sdram ???????????????????? 4 ? rev 1.7 consumer dram jul / 2012 ? nanya technology corp . all rights reserved nanya technology corp. reserves the right to chan ge products and specifications without notice. pin configuration ? 84 balls bga package (x16) < top view> see the balls through the package ? free datasheet http:/// NT5TU64M8DE / nt5tu32m16dg 512mb ddr2 sdram ???????????????????? 5 ? rev 1.7 consumer dram jul / 2012 ? nanya technology corp . all rights reserved nanya technology corp. reserves the right to chan ge products and specifications without notice. input / output functional description symbol type function ck, ck input clock: ck and ck are differential clock inputs. all addre ss and control input signals are sampled on the crossing of the positive edge of ck and negative edge of ck . output (read) data is referenced to the crossings of ck and ck (both directions of crossing). cke input clock enable: cke high activates, and cke low deactiva tes, internal clock signals and device input buffers and output drivers. taking ck e low provides precharge power-down and self-refresh operation (all banks idle), or active power-down (row active in any bank). cke is synchronous for power down entry and exit and for self-refresh entry. cke is asynchronous for self-refresh exit. after v ref has become stable during the power on and initialization sequence, it must be maintained for proper operation of the cke receiver. for proper self-refresh entry and exit, v ref must maintain to this input. cke must be maintained high throughout read and write accesses. input buffers, excluding ck, ck , odt and cke are disabled during power down. input buffers, excluding cke, are disabled during self-refresh. cs input chip select: all commands are masked when cs is registered high. cs provides for external rank selection on systems with multiple memory ranks. cs is considered part of the command code. ras , cas , we input command inputs: ras , cas and we (along with cs ) define the command being entered. dm, ldm, udm input input data mask: dm is an input mask signal for write data. input data is masked when dm is sampled high coincident with that input data durin g a write access. dm is sampled on both edges of dqs. although dm pins are input only, t he dm loading matches the dq and dqs loading. for x8 device, the function of dm or rdqs / rqds is enabled by emrs command. ba0 ? ba1 input bank address inputs: ba0 and ba1 define to which bank an active, read, write or precharge command is being applied. bank address also deter mines if the mode register or extended mode register is to be accessed during a mrs or emrs cycle. a0 ? a13 input address inputs: provides the row address for activa te commands and t he column address and auto precharge or read/write commands to select one location out of the memory array in the respective bank. a10 is sampled during a pr echarge command to determine whether the precharge applies to one bank (a10=low) or all banks (a10=high). if only one bank is to be precharged, the bank is selected by ba0-ba1. th e address inputs also provide the op-code during mode register set commands.a13 row address use on x8 components only. dq input/output data inputs/output: bi-directional data bus. dqs, ( dqs ) ldqs, ( ldqs ), udqs,( udqs ) input/output data strobe: output with read data, input with write data. edge aligned with read data, centered with write data. for the x16, ldqs corresponds to the data on dq0 - dq7; udqs corresponds to the data on dq8-dq15. the data strobes dqs, ldqs, udqs, and rdqs may be used in single ended mode or paired with the optional complementary signals dqs , ldqs , udqs to provide differential pair signaling to the system during bo th reads and writes. an emrs(1) control bit enables or disables the comp lementary data strobe signals. free datasheet http:/// NT5TU64M8DE / nt5tu32m16dg 512mb ddr2 sdram ???????????????????? 6 ? rev 1.7 consumer dram jul / 2012 ? nanya technology corp . all rights reserved nanya technology corp. reserves the right to chan ge products and specifications without notice. symbol type function rdqs, ( rdqs ) input/output read data strobe: for x8 components a rdqs and rdqs pair can be enabled via emrs(1) for real timing. rdqs and rdqs is not support x16 components. rdqs and rdqs are edge-aligned with real data. if enable rdqs and rdqs then dm function will be disabled. odt input on die termination: odt (registered high) enables termination resistance internal to the ddr2 sdram. when enabled, odt is applied to each dq, dqs, dqs , rdqs, rdqs , and dm signal for x8 configuration. for x16 configurat ion odt is applied to each dq, udqs, udqs , ldqs, ldqs , udm and ldm signal. the odt pin will be ignored if the emrs (1) is programmed to disable odt. nc no connect: no internal electric al connection is present. v ddq supply dq power supply: 1.8v 0.1v v ssq supply dq ground v ddl supply dll power supply: 1.8v 0.1v v ssdl supply dll ground v dd supply power supply: 1.8v 0.1v v ss supply ground v ref supply sstl_1.8 reference voltage free datasheet http:/// NT5TU64M8DE / nt5tu32m16dg 512mb ddr2 sdram ???????????????????? 7 ? rev 1.7 consumer dram jul / 2012 ? nanya technology corp . all rights reserved nanya technology corp. reserves the right to chan ge products and specifications without notice. ordering information green standard grade organization part number package speed clock (mhz) cl-t rcd -t rp NT5TU64M8DE ? 3c 60-ball bga 333 5-5-5 NT5TU64M8DE ? ac 400 5-5-5 nt5tu32m16dg ? 3c 84-ball bga 333 5-5-5 nt5tu32m16dg ? ac 400 5-5-5 nt5tu32m16dg ? bd 533 6-6-6 nt5tu32m16dg ? be 533 7-7-7 industrial grade organization part number package speed clock (mhz) cl-t rcd -t rp NT5TU64M8DE ? 3ci 60-ball bga 333 5-5-5 NT5TU64M8DE ? aci 400 5-5-5 nt5tu32m16dg ? 3ci 84-ball bga 333 5-5-5 nt5tu32m16dg ? aci 400 5-5-5 free datasheet http:/// NT5TU64M8DE / nt5tu32m16dg 512mb ddr2 sdram ???????????????????? 8 ? rev 1.7 consumer dram jul / 2012 ? nanya technology corp . all rights reserved nanya technology corp. reserves the right to chan ge products and specifications without notice. block diagram (64mb x 8) " e e s f t t 3 f h j t u f s 3 p x " e e s f t t . 6 9 3 f g s f t i $ p v o u f s 3 f b e - b u d i % s j w f s t 3 f d f j w f s t 0 % 5 $ p o u s p m free datasheet http:/// NT5TU64M8DE / nt5tu32m16dg 512mb ddr2 sdram ???????????????????? 9 ? rev 1.7 consumer dram jul / 2012 ? nanya technology corp . all rights reserved nanya technology corp. reserves the right to chan ge products and specifications without notice. block diagram (32mb x 16) free datasheet http:/// NT5TU64M8DE / nt5tu32m16dg 512mb ddr2 sdram ???????????????????? 10 ? rev 1.7 consumer dram jul / 2012 ? nanya technology corp . all rights reserved nanya technology corp. reserves the right to chan ge products and specifications without notice. functional description the 512mb ddr2 sdram is a high-speed cmos, dynamic random-access memory containing 536,870,912 bits. the 512mb ddr2 sdram is internally configured as a quad-bank dram. read and write accesses to the ddr2 sdra m are burst oriented; accesses start at a selected location and continue for the burst length of four or eight in a programmed sequence. accesses begin with the registration of an activate command, which is followed by a read or write command. the address bits registered coincident with the activate command are used to select the bank and row to be accesses (ba0 and ba1 select the banks, a0-a13 select the row for x8 components, a0-a12 select the row for x16 components). the addr ess bits registered coincident with the read or write command are used to select the starting column location fo r the burst access and to determine if the auto-precharge command is to be issued. prior to normal operation, the ddr2 sdram must be initiali zed. the following sections provide detailed information covering device initialization, register defini tion, command description and device operation. power-up and initialization ddr2 sdrams must be powered up and initialized in a predefin ed manner. operational proc edures other than those specified may result in undefined operation. the following sequence is required for power up and initialization. 1. either one of the following s equence is required for power-up. while applying power, attempt to maintain cke below 0.2 x v ddq and odt at a low state (all other inputs may be unde- fined) the vdd voltage ramp time must be no greater than 200ms from when vdd ramps from 300mv to vdd min; and during the vdd voltage ramp up, ivdd-vddqi 0.3 volts. once the ramp ing of the supply voltages is complete (when vddq crosses vddq min), the supply voltage specificat ions in re-commanded dc operating conditions table. - vdd, vddl, and vddq are driven from a signal power converter output, and - vtt is limited to 0.95v max, and - vref tracks vddq/2; vref must be within 300mv wi th respect to vddq/2 during supply ramp time. - vddq>=vref must be met at all times. while applying power, attempt to maintain cke below 0.2 x vddq and odt at a low stat e, all other inputs may be undefined, voltage levels at i/os and out puts must be less than vddq during voltage ramp time to avoid dram latch-up. during the ramping of the supply voltages, vdd vddl vddq must be maintained and is applicable to both ac and dc levels until the ramping of the supply voltages is complete, which is when vddq crosses vddq min. once the ramping of the supply voltages is complete, the supply voltage specifications provided in re-commanded dc operating conditions table. - apply vdd/vddl before or at the same time as vddq. - vdd/vddl voltage ramp time must be no greater th an 200ms from when vdd ramps from 300mv to vddmin. - apply vddq before or at the same time as vtt. free datasheet http:/// NT5TU64M8DE / nt5tu32m16dg 512mb ddr2 sdram ???????????????????? 11 ? rev 1.7 consumer dram jul / 2012 ? nanya technology corp . all rights reserved nanya technology corp. reserves the right to chan ge products and specifications without notice. - the vddq voltage ramp time from when vdd min is ac hieved on vdd to when vddq min is achieved on vddq must be no greater than 500ms. (note: while vdd is ramping, current may be supplied from vdd through the dram to vddq.) - vref must track vddq/2; vref must be within 300m v with respect to vddq/2 during supply ramp time. - vddq vref must be met at all time. - apply vtt. 2. start clock (ck, ck ) and maintain stable condition. 3. for the minimum of 200us after stable power (vdd, vddl, vddq, vref, and vtt are between their minimum and maximum values as stated in re-commanded dc operating conditions table, and stabl e clock, then apply nop or deselect & take cke high. 4. waiting minimum of 400ns then issue pre-charge all command. nop or deselect applied during 400ns period. 5. issue an emrs command to emr (2). (provide low to ba0, and high to ba1). 6. issue an emrs command to em r (3). (high to ba0 and ba1). 7. issue emrs to enable dll. (provide low to a0, high to ba0 and low to ba1 and a13. and a9=a8=a7=low must be used when issuing this command.) 8. issue a mode register set command for dll re set. (provide high to a8 and low to ba0 and a13) 9. issue a precharge all command. 10. issue 2 more auto-refresh commands. 11. issue a mrs command with low to a8 to initialize devi ce operation (i.e. to program operating parameters without resetting the dll.) 12. at least 200 clocks after step 7, ex ecute ocd calibration (off chip driver impedance adjustment). if ocd calibration is not used, emrs to emr (1) to set ocd calibration default (a9=a8=a7=high) followed by emrs to emr (1) to exit ocd calibration mode (a9=a8=a7=low) must be issued with other operating parameters of emr(1). 13. the ddr2 dram is now ready for normal operation. * to guarantee odt off, vref must be valid and a low level must be applied to the odt pin. example: $ , $ , t u " v u p s f g s f t i mrs 1 3 & " - - emrs $ . % o e " v u p s f g s f t i trp trp trfc trfc extended mode register set with dll enable mode register set with dll reset 1 3 & " - - tmrd tmrd min. 200 cycles to lock the dll $ , & $ p n n b o e 400 ns . 3 4 nop tmrd & |